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Microchip Technology /ATSAME70J21B /SCB /CLIDR

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Interpret as CLIDR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (LEVEL_1)LoC0 (LEVEL_1)LoU

LoC=LEVEL_1, LoU=LEVEL_1

Description

Cache Level ID Register

Fields

LoC

Level of Coherency

0 (LEVEL_1): if neither instruction nor data cache is implemented

1 (LEVEL_2): if either cache is implemented
LoU

Level of Unification

0 (LEVEL_1): if neither instruction nor data cache is implemented

1 (LEVEL_2): if either cache is implemented

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data